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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Features
* Supports AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced for DS1 interfaces and for ETSI ETS 300 011, TBR 4, TBR 12, and TBR 13 for E1 interfaces * Supports ITU-T G.812 Type IV clocks for 1.544kbit/s interfaces and 2.048kbit/s interface
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Introduction
PT7A4410/4410L employs a digital phase-locked loop (DPLL) to provide timing and synchronizing signals for multitrunk T1 and E1 primary rate transmission links, and for STS-3/OC3 links. The STBUS clock and framing signals are phase-locked to input reference signals of either 2.048 MHz, 1.544MHz or 8 kHz. The PT7A4410/4410L meets the requirements for AT&T TR62411 Stratum 3, 4 and Stratum 4 Enhanced, and ETSI ETS 300 011 in jitter tolerance, jitter transfer, intrinsic jitter, frequency accuracy, holdover accuracy, capture range, phase slope and MTIE, etc. The PT7A4410/4410L operates in Manual or Automatic Mode, and in each of the modes, three operating states are available: Normal, Holdover and FreeRun.
Provides C1.5, C3, C2, C4, C8, C6, C16 and C19 output clock signals Provides five kinds of 8kHz ST-BUS framing signals Two independent reference inputs Input reference frequency 1.544MHz, 2.048MHz or 8kHz selectable Provides bit error free reference switching and meets phase slope and MTIE requirements Normal, Holdover or Free-Run operating modes available Holdover accuracy: 0.2ppm Automatic reference input impairment monitor Power supply: 5V (4410) and 3.3V(4410L)
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Applications
* Synchronization and timing control for multitrunk T1 and E1 systems, STS-3/OC3 systems
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Ordering Information
Pa r t Nu m b er PT7A4410J PT7A4410LJ Pa ck a ge 44-Pin PLCC 44-Pin PLCC
ST-BUS clock and frame pulse sources Primary Trunk Rate Converters
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Contents
Features ....................................................................................................................................................... 1 Applications ................................................................................................................................................ 1 Introduction ................................................................................................................................................. 1 Ordering Information .................................................................................................................................. 1 Block Diagram ............................................................................................................................................ 3 Pin Information ........................................................................................................................................... 4 Pin Assignment ..................................................................................................................................... 4 Pin Configuration ................................................................................................................................. 4 Pin Description ..................................................................................................................................... 5 Functional Description ................................................................................................................................ 7 Overall Operation ................................................................................................................................. 7 Modes and States of Operation ........................................................................................................... 10 Applications Information .................................................................................................................... 14 Detailed Specifications .............................................................................................................................. 16 Definitions of Critical Performance Specifictions ............................................................................... 16 Absolute Maximum Ratings ............................................................................................................... 18 Recommended Operating Conditions ................................................................................................. 18 DC Electrical and Power Supply Characteristics ................................................................................ 19 AC Electrical Characteristics .............................................................................................................. 20 Mechanical Specifications ......................................................................................................................... 33 Note .......................................................................................................................................................... 34
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Block Diagram
Figure 1. Block Diagram
RST
TCLR
VCC
GND
OSCi OSCo TCK TDI TMS TRST TDO PRI SEC
Master Clock
TIE Corrector
Virtual Reference DPLL
APLL
IEEE 1149.1a
State Select Reference Select MUX
State Select Input Impairment Monitor
Output Interface Circuit
TIE Correct Enable
ACKi ACKo C1.5 C2 C3 C4 C6 C8 C16 C19 F0 F8 F16 RSP TSP
RSEL LOS1 LOS2
Mode/State Control Machine
Guard Time Circuit
Feedback Frequency Select MUX
HOLDOVER
MS1
MS2
GTo
GTi
FS1
FS2
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Pin Information
Pin Assignment
Table 1. Pin Assignment
G r ou p Chip Clock Power & Ground Clock and Framing Outputs Control Signals Reference Inputs IEEE 1149.1a
Symb ol OSCi, OSCo, ACKi, ACKo VCC, AVDD, GND, AGND C1.5, C3, C2, C4, C6, C8, C16, C19, F0, F8, F16, RSP, TSP RSEL, LOS1, LOS2, MS1, MS2, GTi, GTo, FS1, FS2, RST, TCLR PRI, SEC TCK, TDI, TMS, TRST, TDO
F u n ct ion Clock Power Clock and Framing Signals Control Reference Clock IEEE 1149.1a Interface
Pin Configuration
Figure 2. Pin Configuration
6
4
3
2
1
44
43
42
41
VCC OSCo OSCi AGND F16 RSP F0 TSP F8 C1.5 AVDD
40
5
PRI SEC TRST TCLR TCK GND TMS RST TDI FS1 FS2
7 8 9 10 11 12 13 14 15 16 17 20 21 22 23 24 25 26 27 18 19 28
39 38 37 36
44-Pin PLCC
35 34 33 32 31 30 29
TEST RSEL MS1 MS2 TDO LOS1 LOS2 GTo GND GTi HOLDOVER
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C3 C2 C4 C19 ACKi GND ACKo C8 C16 C6 VCC
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Pin Description
Table 2. Pin Description
P in 1, 23, 31 10 2 Na m e GND AGND TCK Typ e Ground Digit a l G r ou n d (0V) Ground An a log G r ou n d I Test C lock (T T L I n p u t ): Provides the clock to the JTAG test logic. This pin is internally pulled up to VCC. T I E cir cu it r eset (T T L ): A low level on this pin will reset the TIE circuit, re-aligning the output signals with the input signal. TCLR must be active (low) for at least 300ns. This pin is internally pulled down to GND. Test R eset (T T L I n p u t ): Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin is internally pulled down to GND. Secon d a r y r efer en ce (T T L ): One of two independent input reference signals, internally pulled down to GND. P r im a r y r efer en ce (T T L ): The other independent reference signal, internally pulled down to GND. Power su p p ly +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ O scilla t or m a st er clock ou t p u t (C MO S): Output of 20MHz master clock O scilla t or m a st er clock in p u t (C MO S): Input of 20MHz master clock (can be connected directly to a clock source) F r a m e p u lse ST-BUS 16.384Mb /s (C MO S): 8kHz frame signal with 61ns low level pulse that marks the beginning of a ST-BUS frame, typically used for ST-BUS opetation at 8.192Mb/s. See figure 18. R eceive Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the end of an ST-BUS frame. See Figure 19. F r a m e p u lse ST-BUS 2.048 Mb /s (C MO S): 8kHz frame signal with 244ns low level pulse that marks the beginning of a ST-BUS frame e, typically used for ST-BUS opetation at 2.048Mb/s. See figure 18. Tr a n sm it Syn c P u lse (C MO S O u t p u t ). This is an 8kHz 488ns active high framing pulse, which marks the beginning of an ST-BUS frame. See Figure 19. F r a m e p u lse ST-BUS 8.192 Mb /s (C MO S): 8kHz frame signal with 122ns high level pulse that marks the beginning of a ST-BUS frame 1.544 MH z clock (C MO S): This output is used in T1 applications. An a log Power Su p p ly: +5V DC for PT7A4410J. +3.3V DC for PT7A4410LJ 3.088 MH z clock (C MO S): This output is used in T1 applications. 2.048 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s. 4.096 MH z clock (C MO S): This output is used for ST-BUS operation at 2.048Mb/s and 4.096Mb/s. C lock 19.44MH z (C MO S O u t p u t ). This output is used in OC3/STS-3 applications. An a log P L L C lock I n p u t (C MO S I n p u t ). This input clock is a reference for an internal analog PLL. This pin is internally pulled down to GND. An a log P L L C lock O u t p u t (C MO S O u t p u t ). This output clock is generated by the internal analog PLL. Descr ip t ion
3
TCLR
I
4 5 6 7, 28 8 9
TRST SEC PRI VCC OSCo OSCi
I I I Power O I
11
F16
O
12
RSP
O
13
F0
O
14 15 16 17 18 19 20 21 22 24
TSP F8 C1.5 AVDD C3 C2 C4 C19 ACKi ACKo
O O O Power O O O O I O
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Table 2. Pin Description (continued)
P in 25 26 27 29 Na m e C8 C16 C6 HOLDOVER Typ e O O O O Descr ip t ion 8.192 MH z clock (C MO S): This output is used for ST-BUS operation at 8.192Mb/s. 1 6 . 3 8 4 M H z c l o c k ( C M O S ) : T h i s o u t p u t i s u s e d f o r S T- BU S o p e r a t i o n w i t h a 16.384MHz clock. C lock 6.312 MH z (C MO S O u t p u t ). This output is used for DS2 applications. H old over (C MO S O u t p u t ). This output goes to a logic high whenever the digital PLL goes into holdover mode. G u a r d Tim e (Sch m it t in p u t ): The signal at this pin is used by the device's state machine in both Manual and Automatic modes to effect the TIE function and the state changes between Primary Holdover and Primary Normal, and Primary Holdover and Secondary Normal. Refer to Tables 6 and 7. The signal at this pin is clocked in by the rising edge of F8. G u a r d Tim e (C MO S): The LOS1 input is clocked in by the rising edge of F8, then buffered and sent to GTo when in Automatic Mode. This pin is typically used to drive GTi input through an RC circuit. Secon d a r y R efer en ce L oss (T T L ): This pin is normally connected to an external source that applies high logic level whenever the secondary reference signal is lost or invalid. The existing level at this pin is clocked in by the rising edge of F8. This pin is internally pulled down to GND. P r im a r y R efer en ce L oss (T T L ): A high level is applied on this pin when the Primary reference signal is lost or invalid. Refer to pin description of LOS2. This pin is internally pulled down to GND. Test Ser ia l Da t a O u t (T T L O u t p u t ). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enable. M od e/C on t r ol Select 2 (T T L ): Along with MS1, determines the operating modes (Manual or Automatic) and operating states when in Maunal mode (Normal, Holdover or Free-Run). Mod e/C on t r ol Select 1 (T T L ): Refer to pin description of MS2. This pin is internally pulled down to GND. R efer en ce Sou r ce Select (T T L ): In Manual mode, low logic level at this pin selects the Primary Reference as the input reference signal and a high level selects the Secondary. For Automatic mode, this pin must always be maintained at low logic level. This pin is internally pulled down to GND. Test (T T L I n p u t ). This input is normally tied low. When pulled high, it enables internal test modes. This pin is internally pulled down to GND. F r eq u en cy Select 2 (T T L ):Together with FS1, selects one of the three DPLL feedback frequencies to match the desired Input Reference Frequency (8 kHz, 1.544 MHz or 2.048 MHz). F r eq u en cy Select 1 (T T L ): Refer to the pin description of FS2. Test Ser ia l Da t a I n (T T L I n p u t ). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to VCC.. R eset (Sch m it t ): RST Resets the device when at low logic level. Reset is needed whenever the operating mode is changed, or the reference signal frequency is switched or when power-up; so as to ensure proper operation of the device. Following Reset, the output clocks and frame signals are phase-aligned with the input reference source. Test Mod e Select (T T L I n p u t ). JTAG signal that controls the state transitions of the TAP controller. This pin is internally pulled up to VCC..
30
GTi
I
32
GTo
O
33
LOS2
I
34
LOS1
I
35
TDO
O
36
MS2
I
37
MS1
I
38
RSEL
I
39
TEST
I
40 41 42
FS2 FS1 TDI
I I I
43
RST
I
44
TMS
I
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Functional Description
Overall Operation
The PT7A4410/4410L is a multitrunk synchronizer that provides the clock and frame signals for T1 and E1 primary rate digital transmission links, and STS-3/OC3 links. It basically consists of the Clock Generator, Mode/State Control Machine, Time Interval Error (TIE) Corrector, Digital PhaseLocked Loop (DPLL), Analog Phase- Locked Loop (APLL), Input Impairment Monitor and Output Interface Circuit. The DPLL circuit provides synchronization of the output signals with any given input reference signal, and the TIE circuit ensures phase continuity whenever the input reference signal source is changed. Referring to the block diagram on Page 3, the detailed functions of the PT7A4410/4410L are described as follows. Master Clock The PT7A4410/4410L uses either an external clock source or an external crystal and a few discrete components with its internal oscillator as the master clock. Reference Select MUX The PT7A4410/4410L accepts two independent reference signals, the primary reference and secondary reference. Either one of them is selected by the Reference Select MUX circuit and sent to the TIE circuit. The selection is decided according to the availability and quality of the reference signals, the mode operation, and State. Refer to Tables 3, 6 and 7. Figure 3. TIE Corrector
TCLR
Feedback Frequency Select MUX The feedback frequency is selected by FS1 and FS2 (as shown in Table 3) to match the particular incoming reference frequency (1.544MHz, 2.048MHz or 8kHz). A reset (RST) must be performed after every frequency select input change. Table 3. Feedback Frequency Selection
F S2 0 0 1 1
F S1 0 1 0 1
I n p u t F r eq u en cy Reserved 8kHz 1.544MHz 2.048MHz
Time Interval Error (TIE) Corrector The purpose of the TIE corrector is to allow the phase of the output signals to be constant while switching between two mutually incoherent reference signal input sources. Whenever a new input reference signal is selected, the TIE corrector measures the phase difference between it and the feedback signal and aligns them using a variable delay circuit. Thus, the TIE Corrector output a virtual reference input signal for the DPLL that has the same phase as it had for the previous reference signal input source. Thus, the PT7A4410/4410L provides a totally seamless ("glitch-free") transition from one reference signal to another. The TIE Corrector diagram is shown in Figure 3.
PRI or SEC From Select MUX
Comparing Circuit
Delay Value
Programmable Delay Circuit
Virtual Reference Signal To DPLL
Feedback Signal From Frequency Select MUX
TIE Corrector Enable From Mode/State Machine
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Whenever there is a change in the input reference source, such as a switch from the primary reference signal (PRI) to secondary reference signal (SEC), the typical result is a step change in phase of the DPLL input signal that causes an unacceptable step change in the DPLL input signal phase. The TIE Corrector circuit is used to eliminate the step change in the DPLL input signal phase, thus maintaining continuity of phase at the DPLL output. Referring to Figure 3, the selected reference signal (e.g. SEC) feeds the Comparing Circuit where it is compared with the feedback signal from the output circuit. Whenever there is a step change in the reference input signal's phase, the Comparing Circuit will generates a Delay Value for the Programmable Delay Circuit. The Delay Circuit then delays the input reference signal by the Delay Value, thus providing the DPLL with a Virtual Reference Signal having no phase discontinuity. The DPLL phase detects and tracks the Virtual Reference Signal. As the Virtual Reference Signal exhibits no discontinuity of phase, there is no phase transient in the DPLL output signal. This is the Normal operation of the device. During the input reference signals source switching process, a holdover state will occurr before the DPLL begins to track the Virtual Reference Signal. When the input reference is switched to the new source, the State Machine initiates Holdover State, during which the DPLL does not use the Virtual Reference Signal. Instead, it uses stored information to produce a clock signal that is compared in the Comparing Circuit with the Feedback Signal. This compared result is sent to the Programmable Delay Circuit which in turn delivers to the DPLL input a new Virtual Reference Signal whose phase is aligned with that of the previous input reference signal. The State Machine then terminates Holdover State and return the device to Normal state.
As the Programmable Delay Circuit maintains the phase of the Virtual Reference Signal while the TIE Corrector is enabled, there will in general be a time delay between the chip output signals and the selected input reference signal after switching to a new input reference source (e.g. from PRI to SEC). Each time a new reference source is selected, there will in general be a new time delay. The value of this delay represents the accumulation of the phase errors measured and corrected for during the various reference source switching events. The Programmable Delay Circuit can be zeroed through the TCLR pin (low level, min. duration 300ns), realigning the output signals with the present input reference signal. The speed of realignments is limited by the Limiter in the DPLL to 5ns per 125s. Convergence is in the direction of least phase travel. Digital Phase-Locked Loop (DPLL) The DPLL consists of the Phase Detector, Limiter, Loop Filter, Digitally Controlled Oscillator (DCO) and Control Circuit. See Figure 4 for the block diagram of DPLL. The Virtual Reference Signal from TIE is sent to Phase Detector for comparison with the Feedback Signal from the Feedback Frequency Select MUX. An error signal corresponding to their instantaneous phase difference is produced and sent to the Limiter. The Limiter amplifies this error signal to ensure the DPLL responds to all input transient conditions with a maximum output phase slope of 5ns per 125s. This performance easily meets the maximum phase slope of 7.6ns per 125s or 81ns per 1.326ms specified by AT&T TR62411. The Loop Filter is a 1.9Hz low pass filter for all three reference frequency selections: 8kHz, 1.544MHz and 2.048MHz. The filter ensures that the jitter transfer requirements in ETS 300011 and AT&T TR62411 are met.
Figure 4. Block Diagram of DPLL
Virtual Reference from TIE Corrector
Phase Detector
Limiter
Loop Filter DCO DPLL Reference to Output Interface Circuit
Control Circuit
Feedback Signal From Frequency Select MUX
State Select From Input Impairment Monitor
State Select From State Machine
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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The Control Circuit uses signals from the State Machine and Input Impairment Monitor to control the operating states of the DPLL. Three states are available, Normal, Holdover and Free-Run. The Error Signal, after limited and filtered, is sent to Digitally Controlled Oscillator. Based on the processed error value, the DCO will generate the corresponding digital output signals for the Tapped Delay Line in the Output Interface Circuit to produce 12.352MHz, 12.624MHz, 19.44MHz and 16.384MHz signals. The DCO synchronization method depends upon the PT7A4410/4410L operating state, as follows: In Normal state, the DCO generates four output signals which are frequency and phase locked to the selected input reference signal. In Holdover state, the DCO generates four output signals whose frequencies are equal to what they were for a 30ms period shortly before the end of the last Normal State. In Free-Run state, the DCO is free running with an accuracy equal to that of the OSCi 20MHz source. Output Interface Circuit The Output Interface Circuit consists of the Tapped Delay Lines and E1/T1 Dividers as shown in Figure 5. Figure 5. Block Diagram of Output Interface Circuit
Signals from the DCO are sent to Tapped Delay Lines to generate four clock signals, 16.384MHz, 12.624MHz, 19.44MHz and 12.352MHz, which are divided in the T1 and E1 Dividers respectively to provide needed clock and frame signals. The T1 Divider uses the 12.352MHz signal to generate two clock signals, C1.5 and C3. They have a nominal 50% duty cycle. The DS2 Divider uses 12.624MHz signal to generate clock signal C6. Clock signal C19 is generated from 19.44MHz by tapped Delay Line. The E1 Divider uses the 16.384MHz signal to generate four clock signals and three frame signals, i.e., C2, C4, C8, C16, F0, F8 and F16. The frame signals are generated directly from the C16 signal. The C2, C4, C8 and C16 signals have nominal 50% duty cycle. All the frame and clock outputs are locked to each other for all operating states. They have limited driving capability and should be buffered when driving high capacitance (e.g., 30pF) loads.
Tapped Delay Line
12.352MHz
T1 Divider
C1.5 C3
Signal From DCO
Tapped Delay Line
16.384MHz
E1 Divider
C2 C4 C8 C16 F0 F8 F16 RSP TSP C6
Tapped Delay Line Tapped Delay Line
12.624MHz
DS2 Divider
19.44MHz
C19
ACKi
APLL
ACKo
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Mode/State Control Machine The Mode/State Control Machine determines whether the PT7A4410/4410L operates in Automatic or Manual mode, and whether it is in the Normal, Holdover or Free-Run state. In Automatic Mode, the PT7A4410/4410L selects one of three states, Normal, Holdover or Free-Run State. The sequence is determined by LOS1, LOS2 and GTi signals. In Manual Mode, a single state of operation is selected, in accordance with the MS1, MS2, GTi and RSEL signals. All mode and state changes are synchronous with the rising edge of F8. See the Modes and States of Operation section for complete details. Guard Time Circuit
The Auto-Holdover circuit does not use TIE correction. Therefore, the phase delay between the input and output after switching back to Normal State is preserved (is the same as just prior to the switch to Auto-Holdover). APLL The analog PLL is intended to be used to achieve a 50% Duty cycle output clock. Connecting C19 to ACKi will generate a phase locked 19.44 MHz ACKo output with a nominal 50% duty cycle and a maximum peak-to-peak unfiltered jitter of 0.174 U.I. . The analog PLL has an intrinsic jitter of less than 0.01 U.I. In order to achieve this low jitter level separate pins are provided to power (AVDD, AGND) the APLL.
Modes and States of Operation
The Guard Time Circuit sends control signal (GTi) to Mode/ State Control Machine for control of Modes and States. It has two functions: - enabling/disabling the TIE Corrector (Manual and Automatic) (Refer to Table 6 and 7); - selecting which mode change takes place (Automatic only). Under Automatic Mode and in Primary Normal State, two state changes are possible (not counting Auto-Holdover). They are: - Primary Normal to Primary Holdover, and - Primary Normal to Secondary Normal. The level at the GTi pin determines which state occurs. When - GTi=0, Primary Normal to Primary Holdover, - GTi=1, Primary Normal to Secondary Normal. Input Impairment Monitor This circuit monitors the input signals to the DPLL and automatically enables the Holdover State (Auto-Holdover) when the incoming signal is completely lost, or if its frequency is outside the auto-holdover capture range (either a small or large amount). When the incoming signal returns to normal, the DPLL will be returned to Normal State. Figure 6. Block Diagram of Mode/State Control Machine
To Reference Select MUX RSEL LOS1 LOS2 To Tie Corrector Enable To DPLL State Select To and From Guard Time Circuit
The PT7A4410/4410L operates either in Manual mode or Automatic mode. Each mode has three possible operating states, Normal, Holdover or Free-Run. Shown in Table 4 and Table 5 are the mode and state selection instructions, using pins MS1, MS2, and RSEL. Table 4. Input Reference Selection
Mod es Manual
R SE L 0 1 0
I n p u t R efer en ce PRI SEC Mode/State Machine Control Reserved
Auto 1
Table 5. Operation Modes and States
MS2 0 0 1 1
MS1 0 1 0 1
Mod es Manual Manual Manual Auto
St a t es Normal Holdover Freerun Mode/State Machine Control
Mode/State Control Machine
MS1
MS2 HOLDOVER
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Manual Mode The Manual Operation Mode is used when either very simple control is required, or when complex control is required which is not accommodated by Automatic Mode. For example, Manual Mode can be used in a system requiring only Normal State and only one input stimulus (RSEL). Complex control is used for systems requiring states of operation and more input stimuli. In such cases, external circuitry, typically a microcontroller, is needed. In Manual Mode, one of the three states is selected by MS2 and MS1. The active reference input is selected by the RSEL pin. See Table 4 and Table 5. For the state change situation, refer to Table 6 and Figure 7. Automatic Mode Automatic Mode is used in systems requiring neither very simple nor very complex control, which can be realized by the PT7A4410/4410L in accordance with the State Change Diagram shown in Figure 8. Automatic Mode is also selected by MS2 and MS1 (set 1,1). In this Mode, the PT7A4410/4410L will operate in three states alternatively. The changes of states will follow a sequence automatically under control of LOS1, LOS2 and GTi. See Table 7 and Figure 8 for the state change sequence. Normal State In Normal State, the PT7A4410/4410L output signals are synchronized with one of two input reference inputs. In this state, the input reference signal is used, with or without TIE correction, as reference for the DPLL phase detector.
Holdover State In Holdover State, the output signals of PT7A4410/4410L are not synchronized with the external input reference signal. Instead, they are generated by using the information stored 30ms to 60ms before when the device operated in Normal State. When in Normal Mode, a numerical value corresponding to the output reference frequency is stored alternately in two memory locations every 30ms. When the device is switched into Holdover state, the value in memory from (between 30ms and 60ms) is used to set the output frequency of the device. Generally, the amount of phase drift while in Holdover is negligible because the Holdover State is very accurate. Two factors affect the accuracy of Holdover State. One is drift on the Master Clock while in Holdover State. The change in OSCi accuracy while in Holdover, other than absolute Master Clock (OSCi) accuracy, will affect the holdover accuracy. The other factor is large jitter on the reference input prior (30 to 60ms) to the mode switch. The Holdover State is generally used for short durations, under control of GTi signal, when the synchronization to the input reference is temporarily disturbed. Free-Run State Typically the Free-Run State is used when a master clock is required or immediately following system power-up before network synchronization is achieved. In Free-Run State, the outputs of the PT7A4410/4410L are uncorrelated with the input reference signal and the stored information of output reference. Instead, these output signals are based solely on the master clock frequency (OSCi). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi).
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Table 6. Manual Operation Mode
I n p u t C on t r ol F r ee-R u n MS2 0 0 0 0 0 1 MS1 0 0 0 1 1 0 R SE L 0 0 1 0 1 X G Ti S0 0 1 X X X X S1 S1 S2 / / Nor ma l (P R I ) S1 S2 TIE S1H / S0
St a t e Nor ma l (SE C ) S2 S1 TIE S1 TIE / S2H S0 H old over (P R I ) S1H S1 S1 TIE S2 TIE / S0 H old over (SE C ) S2H S1 TIE S1 TIE S2 TIE / S0
L egen d : -: No change /: Not valid TIE: State change occurs with TIE Corrector circuit. Refer to figure 6 for state changes to and from Auto-Holdover state.
Figure 7. Diagram of State Change in Manual Mode
S0 Free-Run (10X)
S1 Normal Primary (000)
IR
S1A Auto-Holdover Primary (000)
S2A Auto-Holdover Secondary (001)
IR
S2 Normal Secondary (001)
GTi=1 GTi=0
S1H Holdover Primary (010)
S2H Holdover Secondary (011)
Notes: (xxx): (MS2 MS1 RSEL) * Movement to Normal State from any state requires a IR: Invalid Reference Signal valid input signal. : Phase re-alignment : Phase continuity maintained without TIE Corrector : Phase continuity maintained with TIE Corrector
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Data Sheet PT7A4410/4410L T1/E1/OC3 System Synchronizer
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Table 7. Automatic Operation Mode (MS1 MS2=11, RSEL=0)
I n p u t C on t r ol F r ee-R u n L O S2 1 X X 0 0 1 L O S1 1 0 0 1 1 1 G Ti X 0 1 0 1 X R ST S0 0 to 1 1 1 1 1 1 S1 S1 S2 S2 Nor ma l (P R I ) S1 S0 S1H S2 TIE S1H
St a t e Nor ma l (SE C ) S2 S0 S1 TIE S1 TIE S2H H old over (P R I ) S1H S0 S1 S1 TIE S2 TIE H old over (SE C ) S2H S0 S1 TIE S1 TIE S2 TIE S2 TIE -
L egen d : -: No change /: Not valid TIE: State change occurs with TIE Corrector circuit. Refer to figure 7 for state changes to and from Auto-Holdover state.
Figure 8. Diagram of State Change in Automatic Mode
(11X)
(11X) RST=1
Reset
(X0X) (X0X)
S0 Free-Run
(011)
(01X)
(01X) (X0X) (X0X) (01X)
S1 Normal Primary
IR
S1A Auto-Holdover Primary
(X0X) (011) (X0X)
S2A Auto-Holdover Secondary
IR
S2 Normal Secondary
(011) (11X) (11X) (01X)
(X01) (X00)
(010 or 11X)
(010 or 11X)
S1H Holdover Primary
S2H Holdover Secondary
(11X)
(010 or 11X)
Notes: (xxx): (LOS2 LOS1 GTi) IR: Invalid Reference Signal : Phase re-alignment : Phase continuity maintained without TIE Corrector : Phase continuity maintained with TIE Corrector
* Movement to Normal State from any state requires a valid input signal.
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Applications Information
Master Clock The PT7A4410/4410L uses either an external clock source or an external crystal as the master timing source. In Free-Run State, the frequency tolerance of the PT7A4410/ 4410L output clocks are equal to the frequency tolerance of the timing source. In an application, if an accurate Free-Run State is not required, the tolerance of the master timing source may be 100ppm. If required, the tolerance must be no greater than 32ppm. The capture range of PT7A4410/4410L will also be considered when deciding the accuracy of the master timing source. The sum of the accuracy of the master timing source and the capture range of the PT7A4410/4410L will always equal 230ppm. For example, if the master timing source is 100ppm, the capture range will be 130ppm. * Clock Oscillator If using an external clock source, its output pin should be connected directly (not AC coupled) to the OSCi pin of the PT7A4410/4410L and the OSCo pin of PT7A4410/4410L can be left open as shown in Figure 9 or connected as an output pin. Figure 9. Clock Oscillator Connection
PT7A4410/4410L +5V OSCi +5V 20MHz OUT GND
* Crystal Oscillator If a crystal oscillator is selected as the master timing source, it should be connected to the PT7A4410/4410L as shown in Figure 10. Figure 10. Crystal Oscillator Connection
PT7A4410/4410L 20MHz OSCi
1M
56pF
39pF
3-50pF
OSCo
100
The crystal specification is as follows: - Frequency: - Tolerance: - Oscillation Mode: - Resonance Mode: - Load Capacitance: - Maximum Series Resistance: - pproximate Drive Level: Guard Time Adjustment Circuit 20MHz as required Fundamental Parallel 32pF 35 1mW
0.1F
AT&T TR62411 recommends that excessive switching of the timing reference should be minimized. Switching between references should be performed only when the primary signal is degraded. The Holdover State is used to minimize reference source switching (from PRI to SEC). When the PRI signal is degraded, the PT7A4410/4410L enters Holdover State for a predetermined maximum time (i.e., guard time). If the PRI signal returns to normal before the expiration of the guard time (level at GTi pin is low), the PT7A4410/4410L will return to Normal State with PRI input reference. If the PRI signal is still degraded after expiration of the guard time (level at GTi becomes high), the reference switching (from PRI to SEC) will occur.
OSCo No Connection
When selecting the clock oscillator, following specifications should be considered. They are - absolute frequency - frequency change over temperature - output rise and fall time - output level - duty cycle Refer to AC Electrical Characteristics.
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A simple way to control the Guard Time is shown in Figure 11. The Guard Time can be calculated as follows: VCC tGd = RC x ln ( VCC - VSIH
* VSIH is the logic high going threshold for the GTi Schmitt Trigger input, see DC Electrical Characteristics.
) RC x 0.6
In cases where fast toggling of the LOS1 input might be expected, an unsymmetrical Guard Time Circuit is recommended as shown in Figure 12. This setting ensures that reference switching does not occur until the entire guard time has expired. The timing diagram is shown in Figure 13.
Figure 11. Symmetrical Guard Time Circuit
PT7A4410/4410L
Figure 12. Unsymmetrical Guard Time Circuit
PT7A4410/4410L GTo
RC 150k +C 10F RD 1k
GTo
R 150k
+
C 10F
GTi
RP 1k GTi
RP 1k
Figure 13. Timing Example of Unsymmetrical Guard Time Circuit in Automatic Mode
SEC Signal Status LOS2 PRI Signal Status LOS1
Good
Good
Bad TD
Good TD
Bad
Good
GTo VSIH GTi
State
PRI Normal
PRI Holdover
PRI Normal
PRI Holdover
SEC Normal
PRI Normal
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Reset Circuit A simple power up reset circuit with about a 50s reset active (low) time is shown in Figure 14. Resistor RP is for protection only. The reset low time is not critical but should be greater than 300ns. Figure 14. Power-up Reset Circuit
PT7A4410/4410L
Detailed Specifications
Definitions of Critical Performance Specifictions
Intrinsic Jitter: Intrinsic jitter is the jitter produced by the synchronizing circuit. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured when the device is in a non-synchronizing mode - such as free running or holdover - by measuring the output jitter of the device. Intrinsic jitter is usually measured with various band limiting filters depending on the applicable standards. Jitter Tolerance: Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and/or regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is present on its reference. The applicable standard specifies how much jitter to apply to the reference when testing for jitter tolerance. Jitter Transfer: Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device with respect to a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards. Its 3 possible input frequencies and 9 outputs give the PT7A4410/4410L 27 possible jitter transfer combinations. However, only three cases of the jitter transfer specifications are given in the AC Electrical Characteristics; as the remaining combinations can be derived from them. For the PT7A4410/4410L, two internal elements determine the jitter attenuation. They are internal 1.9Hz low pass loop filter and phase slope limiter. The phase slope limiter limits the output phase slope to 5ns/125s. Therefore, if the input signal exceeds this rate, such as for very large amplitude low frequency input jitter, the maximum output phase slope will be limited (i.e., attenuated) to 5ns/125s. It should be noted that 1UI at 1.544MHz (644ns) is not equal to 1UI at 2.048MHz (488ns). A transfer value using different input and output frequencies must be calculated in common units (e.g., seconds) as shown in the following example. Example : When the T1 input jitter is 20UI (T1 UI Units) and the T1 to T1 jitter attenuation is 18dB, The T1 and E1 output jitter can be calculated as follows:
+5V
R 10k RST RP 1k C 10nF
Power Supply Decoupling The PT7A4410/4410L has two VCC pins and two GND pins. Power decoupling capacitors should be included as shown in Figure 15. Figure 15. Power Supply Decoupling
C2 0.1F + 28 31
PT7A4410 /4410L 17 + 10 1 7 + C3 0.1F
C1 0.1F
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JT1o = JT1i x 10
( -A ) 20
= 20 x 10
( -18 ) 20
= 2.5UI
JE1o = JT1o x ( 1UIT1) = JT1o x ( 644ns ) = 3.3UI 488ns 1UIE1 Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. Note that the resulting jitter transfer functions for all combinations of inputs (8kHz, 1.544MHz, 2.048MHz) and outputs (8kHz, 1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, 16.384MHz, 6.312MHz, 19.44MHz) for a given input signal (jitter frequency and jitter amplitude) are the same. Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). Frequency Accuracy: Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. For the PT7A4410/4410L, the Free-Run accuracy is equal to the Master Clock (OSCi) accuracy. Holdover Accuracy: Holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques. For the PT7A4410/4410L the storage value is determined while the device is in Normal State and locked to an external reference signal. The absolute Master Clock (OSCi) accuracy of the PT7A4410/4410L does not affect Holdover accuracy, but the change in OSCi accuracy while in Holdover Mode does. Lock Range: If the PT7A4410/4410L DPLL is already in a state of synchronization ("lock") with the incoming reference signal, it is able to track this signal to maintain lock as its frequency varies over a certain range, called the Lock Range. The size of Lock Range is related to the range of the Digitally Controlled Oscillators and is equal to 230ppm minus the accuracy of the master clock (OSCi). For example, a 32ppm master clock results in a Lock Range of 198ppm.
Capture Range: The PT7A4410/4410L DPLL is not at present in a state of synchronization (lock) with the incoming reference signal, it is able to initiate (acquire) lock only if the signal's frequency is within a certain range, called the Capture Range. For any PLL, no portion of the Capture Range can fall outside the Lock Range, and, in general, the Capture Range is more narrow than the Lock Range. However, owing to the design of its Phase Detector, the PT7A4410/4410L's Capture Range is equal to its Lock Range. Phase Slope: Phase slope is measured in seconds per second and is the rate at which a given signal changes phase with respect to an ideal signal of constant frequency. The given signal is typically the output signal. The ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. Time Interval Error (TIE): TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE): MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE(S) = TIEmax(t) - TIEmin(t) Phase Continuity: Phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. Usually, the given timing signal and the ideal timing signal are of the same frequency. Phase continuity applies to the output of the synchronizer after a signal disturbance due to a reference source switch or a state change. The observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. For the PT7A4410/4410L, the output signal phase continuity is maintained to within 5ns at the instance (over one frame) of all reference source switches and all state changes. The total phase shift, depending on the switch or type of state change, may accumulate up to 200ns over many frames. The rate of change of the 200ns phase shift is limited to a maximum phase slope of approximately 5ns/125s. This meets the AT&T TR62411 maximum phase slope requirement of 7.6ns/125s (81ns/1.326ms).
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Absolute Maximum Ratings
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Storage Temperature ...................................................... -65oC to +150oC Ambient Temperature with Power Applied ...................... -40oC to +85oC Supply Voltage to Ground Potential (Inputs & VCC Only) ...... -0.3 to 7.0V Supply Voltage to Ground Potential (Outputs & D/O Only) .. -0.3 to 7.0V DC Input Voltage .................................................................. -0.3 to 7.0V DC Output Current ...................................................................... 120mA Power Dissipation ....................................................................... 900mW
Recommended Operating Conditions
Table 8. Recommended Operating Conditions
Sym Descr ip t ion Supply Voltage for 4410 VCC Supply Voltage for 4410L TA Operating Temperature Over Recommended Operating Conditions Test C on d it ion s Min 4.5 3.0 -40 Typ 5.0 3.3 25 Ma x 5.5 3.6 85 Un it s V V
o
C
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DC Electrical and Power Supply Characteristics
Table 9. DC Electrical and Power Supply Characteristics
Sym ICCQ Descr ip t ion Quiescent Power Supply Current 4410L 4410 OSCi = Clock, Note 2 4410L ICC Supply Current 4410 OSCi = Crystal, Note 2 4410L VIH VIL VCIH VCIL VSIH TTL HIGH Input Voltage-All pins except OSCi, RST and GTi TTL LOW Input Voltage-All pins except OSCi, RST and GTi CMOS HIGH Input VoltageOSCi pin CMOS LOW Input VoltageOSCi pin Schmitt HIGH Input VoltageGTi, RST pins Schmitt LOW Input VoltageGTi, RST pins Schmitt Hysteresis VoltageGTi, RST pins Input Leakage Current - Pins: TCK, SEC, PRI, TDI, TMS IIL Input Leakage Current - Pins: TCLR, TRST, ACKi, LOS2, LOS1, MS1, RESL, TEST Input Leakage Current - other pins 4410 VOH VOL HIGH Output Voltage 4410L LOW Output Voltage IOH = -4mA IOL = 4mA 4410 4410L 4410 4410L -10 2.4 2.0 0.8 VI = VCC or 0V 4410 4410L 4410 4410L 0.4 -140 -100 140 100 10 3.6 2.6 1.8 1.1 0.7VCC 0.3VCC 2.0 0.8 40 mA V V V V V V V V V A A A A A V V V 70 mA 35 mA Device 4410 OSCi = 0V, Note 2 10 60 mA mA Test C on d it ion s Min Typ Ma x 20 Un it s mA
VSIL VHYS
Note: 1. Supply voltages and operating temperature are as per Recommended Operating Conditions. 2. MS2 = VCC, FS1 = VCC , FS2= GND, other inputs connected to GND. 3. All outputs are unloaded except for VOH and VOL measurement.
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AC Electrical Characteristics
Performance Table 10. Performance
Sym Descr ip t ion 0ppm Free-Run State Accuracy with OSCi at: 32ppm 100ppm 0ppm Holdover State Accuracy with OSCi at: 32ppm 100ppm 0ppm DPLL Capture Range With OSCi at: 32ppm 100ppm APLL Capture Range Phase Lock Time Output Phase Continuity with: Reference Switch 43 1-3, 6-14 1-3, 6-14 1-2, 4-14 1-4, 6-14 1-3, 6-14 1-3, 6-8 1, 2, 4, 6-8, 40 5-8 Test C on d it ion s* Min 0 -32 -100 -0.2 -0.2 -0.2 -190 -158 -90 10 Typ Ma x 0 +32 +100 +0.2 +0.2 +0.2 +230 +198 +130 30 23 200 200 200 50 600 1-14, 27 Output Phase Slope 8kHz Reference Input for Auto-Holdover with:1.544MHz 2.048MHz 1-3, 6, 9-11 1-3, 7, 9-11 1-3, 8-11 <-30k <-30k <-30k or or or 45 >+30k >+30k >+30k s/s ppm ppm ppm Un it s ppm ppm ppm ppm ppm ppm ppm ppm ppm MHz s ns ns ns ns ns
State Switch to Normal State Switch to Free-Run State Switch to Holdover MTIE (Maximum Time Interval Error)
* Refer to the Test Conditions on Page 32 for details.
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Voltage Levels for Timing Parameter Measurement Table 11. Voltage Levels for Timing Parameter Measurement
Sym VT VHM VLM Descr ip t ion Threshold Voltage Rising and Falling Threshold Voltage High Rising and Falling Threshold Voltage Low Sch mit t 0.5VCC 0.7VCC 0.3VCC TTL 1.5 2.0 0.8 CMOS 0.5VCC 0.7VCC 0.3VCC Un it s V V V
Figure 16. Voltage Levels for Timing Parameter Measurement
Timing Reference Points Signal VHM VT VLM
tIF.tOF
tIR.tOR
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Input and Output Timing Table 12. Input and Output Timing of 4409
Sym tRW tIRF tR8D tR15D tR2D tF0D tF16D tC15D tC6D tC3D tC2D tC4D tC8D tC16D tTSPD tRSPD tC19D tC15W tC3W tC6W tC2W tC4W tC8W
Descr ip t ion Reference Input pulse Width High or Low
Test C on d it ion s*
Min 100
Typ
Ma x
Un it s ns
1-3, 6-11, 39 Reference Input Rising or Falling Time 8kHz Reference Input to F8 Delay 1.544kHz Reference Input to F8 Delay 2.048kHz Reference Input to F8 Delay F8 to F0 Delay F8 to F16 Delay F8 to C1.5 Delay F8 to C6 Delay F8 to C3 Delay F8 to C2 Delay F8 to C4 Delay F8 to C8 Delay F8 to C16 Delay F8 to TSP Delay 1-14, 21, 39 F8 to RSP Delay F8 to C19 Delay C1.5 Pulse Width High or Low C3 Pulse Width High or Low C6 Pulse Width High or Low C2 Pulse Width High or Low C4 Pulse Width High or Low C8 Pulse Width High or Low -10 0 309 149 72 230 111 52 10 52 339 175 86 258 133 70 ns ns ns ns ns ns ns ns 1-14, 21, 39 1-14, 21 1-3, 6-14, 21, 23, 38 -28 337 217 110 19 -45 -8 -46 -10 -10 -10 -10 -10 10 -1 363 238 134 44 -31 9 -31 5 5 5 5 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* Refer to the Test Conditions on Page 32 for details.
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Table 13. Input and Output Timing of 4409L
Sym tRW tIRF tR8D tR15D tR2D tF0D tF16D tC15D tC6D1) tC3D tC2D tC4D tC8D tC16D tTSPD1) tRSPD1) tC19D1) tC15W tC3W tC6W1) tC2W tC4W tC8W Descr ip t ion Reference Input pulse Width High or Low 1-3, 6-11, 39 Reference Input Rising or Falling Time 8kHz Reference Input to F8 Delay 1.544kHz Reference Input to F8 Delay 2.048kHz Reference Input to F8 Delay F8 to F0 Delay F8 to F16 Delay F8 to C1.5 Delay F8 to C6 Delay F8 to C3 Delay F8 to C2 Delay F8 to C4 Delay F8 to C8 Delay F8 to C16 Delay F8 to TSP Delay 1-14, 21, 39 F8 to RSP Delay F8 to C19 Delay C1.5 Pulse Width High or Low C3 Pulse Width High or Low C6 Pulse Width High or Low C2 Pulse Width High or Low C4 Pulse Width High or Low C8 Pulse Width High or Low -10 0 309 149 72 230 111 52 10 52 339 175 86 258 133 70 ns ns ns ns ns ns ns ns 1-14, 21, 39 1-14, 21 1-3, 6-14, 21, 23, 38 -21 345 232 112 19 -47 -9 -49 -11 -11 -11 -11 -10 10 6 371 248 138 44 -31 9 -32 4 4 4 4 10 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Test C on d it ion s* Min 100 Typ Ma x Un it s ns
* Refer to the Test Conditions on Page 32 for details.
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Table 14. Input and Output Timing (Continued)
Sym tC16WL tTSPW tRSPW tC19W tF0WL tF8WH tF16WL tORF tS tH Descr ip t ion C16 Pulse Width Low TSP Pulse Width High 1-14, 21 RSP Pulse Width High C19 Pulse Width High or Low F0 Pulse Width Low F8 Pulse Width High F16 Pulse Width Low Output Clock and Frame Pulse Rising or Falling Time Input Controls Setup Time Input Controls Hold Time 1-14, 21, 39 9 100 100 ns ns ns 478 16 230 111 52 495 36 258 133 70 ns ns ns ns ns Test C on d it ion s* Min 26 478 Typ Ma x 37 494 Un it s ns ns
* Refer to the Test Conditions on Page 32 for details. Figure 17. Input to Output Timing (Normal State, after TCLR or RST)
t R8D
PR I/SE C 8kH z VT
tR W t R15D tR W
VT
PR I/SE C 1.544M H z
t R2D
PR I/SE C 2.048M H z F8
tR W
VT VT
Note: Input to output delay values are valid after a TCLR or RST with no further state changes.
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Figure 18. Output Timing
tF8WH
F8 VT
tF0D tF0WL
F0 VT
tF16D
F16
tF16WL tC16WL tC16D
VT
C16
VT
tC8W
C8
tC8W
tC8D
VT
tC4W
C4
tC4D tC4W tC2D
VT
C2
tC2W
VT
tC3D tC3W
C3
tC3W
VT
tC15W
C1.5
tC15D
VT
tC6W
C6
tC6W
tC6D
VT
tC19W
C19
tC19D
VT
tC19W
Figure 19. Output Timing
F8 C2 tRSPD RSP TSP
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tTSPW tTSPD
tRSPW
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Figure 20. Setup and Hold Timing of Input Controls
F8
VT
tS
MS1,2 LOS1,2 RSEL GTi
tH
VT
Intrinsic Jitter Unfiltered Table 15. Intrinsic Jitter Unfiltered
Sym
Descr ip t ion Instrinsic Jitter at F8 (8kHz) Instrinsic Jitter at F0 (8kHz) Instrinsic Jitter at F16 (8kHz) Instrinsic Jitter at C1.5 (1.544MHz) Instrinsic Jitter at C2 (2.048MHz) Instrinsic Jitter at C3 (3.088MHz) Instrinsic Jitter at C4 (4.096MHz) Instrinsic Jitter at C6 (6.312MHz) Instrinsic Jitter at C8 (8.192MHz) Instrinsic Jitter at C16 (16.384MHz) Instrinsic Jitter at C19 (19.44MHz) Instrinsic Jitter at TSP (8kHz) Instrinsic Jitter at RSP (8kHz)
Test C on d it ion s*
Min
Typ
Ma x 0.0002
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
1-14, 21-24, 28
0.0002 0.0002
1-14, 21-24, 29 1-14, 21-24, 30 1-14, 21-24, 31 1-14, 21-24, 32 1-14, 21-24, 41 1-14, 21-24, 33 1-14, 21-24, 34 1-14, 21-24, 42 1-14, 21-24, 28 1-14, 21-24, 28
0.030 0.040 0.060 0.080 0.120 0.160 0.320 0.230 0.0002 0.0002
* Refer to the Test Conditions on Page 32 for details.
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C1.5 (1.544MHz) Instrinsic Jitter Filtered Table 16. C1.5 (1.544MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
1-14, 21-24, 29 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 32 for details.
0.010 0.005
C2 (2.048MHz) Instrinsic Jitter Filtered Table 17. C2 (2.048MHz) Instrinsic Jitter Filtered
Sym
Descr ip t ion Instrinsic Jitter (4Hz to 100kHz Filter) Instrinsic Jitter (10Hz to 40kHz Filter)
Test C on d it ion s*
Min
Typ
Ma x 0.015 0.010
Un it s UIpp UIpp UIpp UIpp
1-14, 21-24, 30 Instrinsic Jitter (8kHz to 40kHz Filter) Instrinsic Jitter (10Hz to 8kHz Filter)
* Refer to the Test Conditions on Page 32 for details.
0.010 0.005
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8kHz Input to 8kHz Output Jitter Transfer Table 18. 8kHz Input to 8kHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 0.01UIpp Input Jitter Attenuation for 1Hz with 0.54UIpp Input Jitter Attenuation for 10Hz with 0.10UIpp Input Jitter Attenuation for 60Hz with 0.10UIpp Input Jitter Attenuation for 300Hz with 0.10UIpp Input Jitter Attenuation for 3600Hz with 0.005UIpp Input Test C on d it ion s* Min 0 6 12 1-3, 6, 9-14, 21, 22, 24, 28, 35 28 42 45 38 dB dB dB Typ Ma x 6 16 22 Un it s dB dB dB
* Refer to the Test Conditions on Page 32 for details.
1.544MHz Input to 1.544MHz Output Jitter Transfer Table 19. 1.544MHz Input to 1.544MHz Output Jitter Transfer
Sym Descr ip t ion Jitter Attenuation for 1Hz with 20UIpp Input Jitter Attenuation for 1Hz with 104UIpp Input Jitter Attenuation for 10Hz with 20UIpp Input Jitter Attenuation for 60Hz with 20UIpp Input Jitter Attenuation for 300Hz with 20UIpp Input Jitter Attenuation for 10kHz with 0.3UIpp Input Jitter Attenuation for 100kHz with 0.3UIpp Input 1-3, 7, 9-14, 21, 22, 24, 29, 35 Test C on d it ion s* Min 0 6 12 28 42 45 45 Typ Ma x 6 16 22 38 Un it s dB dB dB dB dB dB dB
* Refer to the Test Conditions on Page 32 for details.
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2.048MHz Input to 2.048MHz Output Jitter Transfer Table 20. 2.048MHz Input to 2.048MHz Output Jitter Transfer
Sym Descr ip t ion Test C on d it ion s* 1-3,8,9-14,21,22,24,30,35 Jitter at Output for 1Hz 3.00UIpp Input 1-3,8,9-14,21,22,24,30,36 1-3,8,9-14,21,22,24,30,35 Jitter at Output for 3Hz 2.33UIpp Input 1-3,8,9-14,21,22,24,30,36 1-3,8,9-14,21,22,24,30,35 Jitter at Output for 5Hz 2.07UIpp Input 1-3,8,9-14,21,22,24,30,36 1-3,8,9-14,21,22,24,30,35 Jitter at Output for 10Hz 1.76UIpp Input 1-3,8,9-14,21,22,24,30,36 Jitter at Output for 100Hz 1.50UIpp Input 1-3,8,9-14,21,22,24,30,35 1-3,8,9-14,21,22,24,30,36 1-3,8,9-14,21,22,24,30,35 1-3,8,9-14,21,22,24,30,36 1-3,8,9-14,21,22,24,30,35 1-3,8,9-14,21,22,24,30,36 0.10 0.06 0.05 0.04 0.03 0.04 0.02 UIpp UIpp UIpp UIpp UIpp UIpp UIpp 0.10 0.40 UIpp UIpp 0.10 0.80 UIpp UIpp 0.09 1.3 UIpp UIpp Min Typ Ma x 2.9 Un it s UIpp
Jitter at Output for 2400Hz 1.50UIpp Input
Jitter at Output for 100kHz 0.20UIpp Input
* Refer to the Test Conditions on Page 32 for details.
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8kHz Input Jitter Tolerance Table 21. 8kHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input 1-3,6,9-14,21,22,24-26,28 Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 3600Hz Input 0.15 0.08 0.02 0.01 UIpp UIpp UIpp UIpp Test C on d it ion s* Min 0.80 0.70 0.60 0.20 Typ Ma x Un it s UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 32 for details.
1.544MHz Input Jitter Tolerance Table 22. 1.544MHz Input Jitter Tolerance
Sym Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input 1-3,7,9-14,21,22,24-26,29 Test C on d it ion s* Min 150 140 130 35 25 15 4 1 0.5 Typ Ma x Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
* Refer to the Test Conditions on Page 32 for details.
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2.048MHz Input Jitter Tolerance Table 23. 2.048MHz Input Jitter Tolerance
Sym
Descr ip t ion Jitter Tolerance for 1Hz Input Jitter Tolerance for 5Hz Input Jitter Tolerance for 20Hz Input Jitter Tolerance for 300Hz Input Jitter Tolerance for 400Hz Input Jitter Tolerance for 700Hz Input Jitter Tolerance for 2400Hz Input Jitter Tolerance for 10kHz Input Jitter Tolerance for 100kHz Input
Test C on d it ion s*
Min 150 140 130 50
Typ
Ma x
Un it s UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp UIpp
1-3,8,9-14,21,22,24-26,30
40 20 5 1 1
* Refer to the Test Conditions on Page 32 for details.
OSCi 20MHz Master Clock Input Table 24. OSCi 20MHz Master Clock Input
Sym Descr ip t ion Test C on d it ion s* 15, 18 Tolerance 16, 19 17, 20 Duty Cycle Rising Time Falling Time Min 0 -32 -100 40 Typ Ma x 0 +32 +100 60 10 10 Un it s ppm ppm ppm % ns ns
* Refer to the Test Conditions on Page 32 for details.
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Notes: 1. Voltages are with respect to ground (GND) unless otherwise stated. 2. Supply voltage and operation temperature are as per Recommended Operating Conditions. 3. Timing parameters are as per AC Electrical Characteristics - Voltage Levels for Timing Parameter Measurement.
Test Conditions: 1. PRI reference input selected. 2. SEC reference input selected. 3. Normal State selected. 4. Holdover State selected. 5. Free-Run State selected. 6. 8kHz frequency source selected. 7. 1.544MHz frequency source selected. 8. 2.048MHz frequency source selected. 9. Master clock input OSCi at 20MHz 0ppm. 10. Master clock input OSCi at 20MHz 32ppm. 11. Master clock input OSCi at 20MHz 100ppm. 12. Selected reference input at 0ppm. 13. Selected reference input at 32ppm. 14. Selected reference input at 100ppm. 15. For Free-Run State of 0ppm. 16. For Free-Run State of 32ppm. 17. For Free-Run State of 100ppm. 18. For capture range of 230ppm. 19. For capture range of 198ppm. 20. For capture range of 130ppm. 21. 25pF capacitive load.
22. OSCi Master Clock Jitter is less than 2ns p-p, or 0.04UI p-p where 1UI p-p = 1/20MHz. 23. Jitter on reference input is less than 7ns p-p. 24. Applied jitter is sinusoidal. 25. Minimum applied input jitter magnitude to regain synchronization. 26. Loss of synchronization is obtained at slightly higher input jitter amplitudes. 27. Within 10ms of the state, reference or input change. 28. 1UIpp = 125s for 8kHz signals. 29. 1UIpp = 648ns for 1.544MHz signals. 30. 1UIpp = 488ns for 2.048MHz signals. 31. 1UIpp = 324ns for 3.088MHz signals. 32. 1UIpp = 244ns for 4.096MHz signals. 33. 1UIpp = 122ns for 8.192MHz signals. 34. 1UIpp = 61ns for 16.384MHz signals. 35. No filter. 36. 40Hz to 100kHz bandpass filter. 37. With respect to reference input signal frequency. 38. After a RST or TCLR. 39. Master clock duty cycle 40% to 60%. 40. Prior to Holdover State, device was in Normal State and phase locked. 41. 1UIpp = 162ns for 6.312MHz signals. 42. 1UIpp = 51ns for 19.44MHz signals.
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Mechanical Specifications
Figure 21. 44-pin PLCC
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Note
Pericom Technology Inc.
Email: support@pti.com.cn China: Asia Pacific: U.S.A.: Web-Site: www.pti.com.cn, www.pti-ic.com No. 20 Building, 3/F, 481 Guiping Road, Shanghai, 200233, China Tel: (86)-21-6485 0576 Fax: (86)-21-6485 2181 Unit 1517, 15/F, Chevalier Commercial Centre, 8 Wang Hoi Rd, Kowloon Bay, Hongkong Tel: (852)-2243 3660 Fax: (852)- 2243 3667 2380 Bering Drive, San Jose, California 95131, USA Tel: (1)-408-435 0800 Fax: (1)-408-435 1100
Pericom Technology Incorporation reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. Pericom Technology does not assume any responsibility for use of any circuitry described other than the circuitry embodied in Pericom Technology product. The company makes no representations that circuitry described herein is free from patent infringement or other rights, of Pericom Technology Incorporation.
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